Implementation and performance of composite fast FIR filtering algorithms

This paper provides a technique to derive a new set of fast Finite Impulse Response (FIR) filtering algorithms founded on the combination of filtering algorithms based on short FFT and short length fast FIR filtering algorithms. Such composite algorithms have the potential to reduce the arithmetic complexity and the characteristic to maintain a low processing delay, independent of the filter length. A methodology for an efficient implementation on the Digital Signal Processor (DSP) of these algorithms is proposed by an optimised structuring and organization of data in memory in order to keep the improvement brought by the reduction of the arithmetic complexity without exceeding the DSP resources such as number of pointers registers and memory. The performance is evaluated in number of machine cycles per point computed. The solution exists to complete the generator code built for the basic algorithms by adding macro-instructions written in a “DSP” assembly code