A 1.5V, 1.6Gb/s/pin, 1Gb DDR3 SDRAM with an Address Queuing Scheme and Bang-Bang Jitter Reduced DLL Scheme

Author

Kim, Yang Ki ; Jeon, Young Jin ; Jeong, Byung Hoon ; Heo, Nak Won ; Chang, Soo Bong ; Jung, Han Gyun ; Kim, Doo Young ; Chung, Hoe Ju ; Kim, Chul Soo ; Ko, Seung Bum ; Kyung, Kye Hyun ; Yoo, Jei Hwan ; Cho, Soo In

Author_Institution

Samsung Electron. Co., Hwasung

fYear

2007

Firstpage

182

Lastpage

183

Abstract

A 1.6Gb/s/pin 1Gb DDR3 SDRAM with a CAS latency of 8 at 1.5 V is developed using an 80 nm dual poly CMOS process, which consumes 30 mA of IDD2N and 160 mA of IDD4R. With an address queuing scheme and a self-timed IOSA, IDD4R current can be reduced by 18 mA. To achieve 1.6Gb/s/pin operation, a bang-bang jitter free DLL with a split phase interpolator is employed.

Keywords

CMOS memory circuits; DRAM chips; buffer circuits; delay lock loops; integrated circuit design; jitter; DDR3 SDRAM; address queuing buffer; bang-bang jitter free DLL scheme; bang-bang jitter reduced DLL scheme; bit rate 1.6 Gbit/s; current 160 mA; current 18 mA; self-timed IDD4R current; self-timed IOSA current; size 80 nm; split phase interpolator; storage capacity 1 Gbit; voltage 1.5 V; CMOS process; Clocks; Content addressable storage; Delay lines; Jitter; Random access memory; Registers; SDRAM; Signal generators; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-05-5

Electronic_ISBN

978-4-900784-05-5

Type

conf

DOI

10.1109/VLSIC.2007.4342706

Filename

4342706