Title :
A 2.5mW 80dB DR 36dB SNDR 22MS/s Logarithmic Pipeline ADC
Author :
Lee, Jongwoo ; Park, Sunghyun ; Kang, Joshua ; Seo, Jae-sun ; Anders, Jens ; Flynn, Michael
Author_Institution :
Univ. of Michigan, Ann Arbor
Abstract :
A switched-capacitor logarithmic pipeline ADC scheme that does not require squaring or any other complex analog functions is described. This approach is ideal where a high dynamic range, but not a high peak SNDR, is required. A signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is implemented in 0.18 mum CMOS. The 22 MS/s ADC achieves a measured DR of 80 dB and a measured SNDR of 36 dB, occupies 0.56 mm2, and consumes 2.54 mW from a 1.62 V supply. The measured dynamic range figure of merit is 174 dB.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; pipeline processing; switched capacitor networks; CMOS; compander; dynamic range; gain 174 dB; gain 36 dB; gain 80 dB; power 2.5 mW; size 0.18 mum; switched-capacitor logarithmic pipeline ADC scheme; voltage 1.62 V; Capacitors; Cyclic redundancy check; Dynamic range; Equations; Operational amplifiers; Pipelines; Programmable control; Prototypes; Table lookup; Voltage; Logarithmic ADC; compander and pipeline ADC;
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
DOI :
10.1109/VLSIC.2007.4342711
