DocumentCode :
1570533
Title :
A timing-driven global routing algorithm considering channel density minimization for standard cell layout
Author :
Suzuki, Takeshi ; Koide, Tsushi ; Wakabayashi, Shin´ichi ; Yoshida, Noriyoshi
Author_Institution :
Fac. of Eng., Hiroshima Univ., Japan
Volume :
4
fYear :
1996
Firstpage :
424
Abstract :
This paper presents a new timing-driven global routing method for standard cell layout. The proposed method can explicitly consider the timing constraint between two registers and minimize the channel density under the given timing constraint. First, we determine the initial global routes. Next, we improve the global routes to satisfy the timing constraint between two registers as well as to minimize the channel density. Finally, for each cell row, the nets incident to terminals an the cell row are assigned to channels to minimize the channel density using 0-1 integer linear programming. We also show experimental results of the proposed method implemented on an engineering workstation, which show that the proposed method is quite promising
Keywords :
circuit layout CAD; circuit optimisation; delays; integer programming; integrated circuit layout; iterative methods; linear programming; minimisation of switching nets; network routing; timing; 0-1 integer linear programming; channel density minimization; engineering workstation; interconnection delay; iterative improvement; net assignment; standard cell layout; timing constraint; timing-driven global routing algorithm; Clocks; Delay; Integrated circuit interconnections; Linear programming; Minimization methods; Timing; Upper bound; Very large scale integration; Wire; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
Type :
conf
DOI :
10.1109/ISCAS.1996.541992
Filename :
541992
Link To Document :
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