Algorithm-based low-power DSP system design: methodology and verification

We present a low-power design methodology based on the multirate approach for DSP systems. Since the data rate in the resulting multirate implementation is M-times slower (where M is a positive integer) than the original data rate while maintaining the same throughput rate, we can apply this feature to either the low-power implementation, or the speed-up of the DSP systems. This design methodology provides VLSI designers with a systematic tool to design low-power DSP systems at the algorithmic/architectural level. The proposed low-power multirate design scheme is verified by the implementation of two FIR VLSI chips with different architectures: one is the normal pipelined design and the other is the multirate FIR design with downsampling rate equal to two. Using the CMOS power dissipation model, we can predict that the multirate FIR chip consumes only 29% power of the normal FIR chip given the same throughput rate. The predicted results will be verified by measuring real power consumption of both chips