• DocumentCode
    1570622
  • Title

    Wideband reduced modeling of interconnect circuits by adaptive complex-valued sampling method

  • Author

    Wang, Hai ; Tan, Sheldon X D ; Chen, Gengsheng

  • Author_Institution
    Dept. of Electr. Eng., Univ. of California, Riverside, CA, USA
  • fYear
    2010
  • Firstpage
    31
  • Lastpage
    36
  • Abstract
    In this paper, we propose a new wideband model order reduction method for interconnect circuits by using a novel adaptive sampling and error estimation scheme. We try to address the outstanding error control problems in the existing sampling-based reduction framework. In the new method, called WBMOR, we explicitly compute the exact residual errors to guide the sampling process. We show that by sampling along the imaginary axis and performing a new complex-valued reduction, the reduced model will match exactly with the original model at the sample points. We show theoretically that the proposed method can achieve the error bound over a given frequency range. Practically the new algorithm can help designers choose the best order of the reduced model for the given frequency range and error bound via adaptive sampling scheme. As a result, it can perform wideband accurate reductions of interconnect circuits for analog and RF applications. We compare several sampling schemes such as linear, logarithmic, and recently proposed re-sampling methods. Experimental results on a number of RLC circuits show that WBMOR is much more accurate than all the other simple sampling methods and the recently proposed re-sampling scheme with the same reduction orders. Compared with the real-valued sampling methods, the complex-valued sampling method is more accurate for the same computational costs.
  • Keywords
    integrated circuit interconnections; reduced order systems; sampling methods; WBMOR; adaptive complex-valued sampling method; adaptive sampling; complex valued reduction; error bound; error control problem; error estimation; exact residual errors; frequency range; interconnect circuits; sampling based reduction framework; sampling scheme; wideband model order reduction; wideband reduced modeling; Algorithm design and analysis; Circuit noise; Computational efficiency; Costs; Error correction; Integrated circuit interconnections; RLC circuits; Radio frequency; Sampling methods; Wideband;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific
  • Conference_Location
    Taipei
  • Print_ISBN
    978-1-4244-5765-6
  • Electronic_ISBN
    978-1-4244-5767-0
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2010.5419924
  • Filename
    5419924