Analysis of switched-capacitor and switched-current networks with complete settling assumption

We present a formulation for analyzing switched-capacitor and switched-current networks that is based on an assumption that, the network settles completely during each switching interval. A fast transient analysis of non-linear networks can then be performed since the solution at the end of each switching interval can be obtained without numerical integration. Existing transistor device models may be easily incorporated and their second-order effects (except for the incomplete charging effect) on circuit performance may be simulated. In addition, the small-signal parameters for the device models may be easily extracted for different bias points in each switching interval and the frequency response of the linearized network may be obtained