Title :
Performance analysis of CMOS Mode Locked class E Power Amplifier
Author :
Arora, Pankaj ; Mukherjee, Jayanta ; Agarwal, Vivek
Author_Institution :
Dept. of Syst. & Control, Indian Inst. of Technol., Mumbai, India
Abstract :
The design of Class E Amplifiers is more difficult than other type of amplifiers as it is imposed by time domain constraints. This paper presents the performance analysis of Mode Locked class E Power Amplifiers using State Space Analysis Algorithm. A technique is introduced which is used to curb the negative effect of parasitic resistance of DC Feed Choke and the Power Amplifier operates at 2.4GHz and simulated with a 0.18μm CMOS process at a supply voltage of 2V.
Keywords :
CMOS analogue integrated circuits; power amplifiers; CMOS process; DC feed choke; frequency 2.4 GHz; mode locked class E power amplifier; parasitic resistance; size 0.18 micron; state space analysis; time domain constraint; voltage 2 V; CMOS technology; Inductors; Laser mode locking; Operational amplifiers; Performance analysis; Power amplifiers; Radiofrequency amplifiers; Switches; Switching circuits; Zero voltage switching; CMOS; Class E; State Space; power amplifier;
Conference_Titel :
Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-7771-5
DOI :
10.1109/MWSCAS.2010.5548651
