• DocumentCode
    1570900
  • Title

    A 1.2-V 77-dB 7.5-MHz Continuous-Time/Discrete-Time Cascaded ΣΔ Modulator

  • Author

    Kulchycki, S.D. ; Trofin, Roxana ; Vleugels, Katelijn ; Wooley, Bruce A.

  • Author_Institution
    Stanford Univ., Stanford
  • fYear
    2007
  • Firstpage
    238
  • Lastpage
    239
  • Abstract
    A hybrid ΣΔ modulator combines the anti-aliasing filtering and high sampling rate advantages of a continuous-time first stage with a low-power discrete-time second stage. A 0.18-μm CMOS experimental prototype samples signals at 240 MHz and achieves 77 dB of dynamic range and a peak SNDR of 67 dB for a signal bandwidth of 7.5 MHz, while dissipating 63.6 mW of analog power from a 1.2-V supply.
  • Keywords
    CMOS integrated circuits; delta-sigma modulation; filtering theory; modulators; antialiasing filtering; bandwidth 7.5 MHz; continuous-time modulator; discrete-time modulator; high sampling rate; hybrid ΣΔ modulator; noise figure 77 dB; power 63.6 mW; size 0.18 μm; voltage 1.2 V; Bandwidth; Broadband amplifiers; CMOS technology; Circuit noise; Delta-sigma modulation; Dynamic range; Filtering; Prototypes; Quantization; Sampling methods; A/D conversion; broadband ADC; cascaded ΣΔ modulator; continuous-time ΣΔ modulator; high-resolution ADC;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2007 IEEE Symposium on
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-4-900784-04-8
  • Electronic_ISBN
    978-4-900784-05-5
  • Type

    conf

  • DOI
    10.1109/VLSIC.2007.4342733
  • Filename
    4342733
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1570900