Parasitics nonlinearity cancellation technique for split DAC architecture by using capacitive charge-pump

A voltage feedback charge-cancellation technique is proposed which prevents the conversion nonlinearity due to the parasitic effect of split DAC architecture in Successive Approximation Register (SAR) ADCs. A voltage feedback network operating as a capacitive charge-pump can efficiently detect and compensate the voltage error in each bit cycling, thus the conversion accuracy can be significantly improved. A 10b 80MS/s SAR ADC was demonstrated in 65nm CMOS technology. Simulation results show that the proposed charge-cancellation technique can improve the Effective Number of Bits (ENOB) from 8.5b to 9.6b and decrease the maximum DNL and INL from 3LSB to 0.5LSB and 1.65LSB to 0.74LSB, respectively, with only 100 μW power dissipation.