DocumentCode
1570928
Title
A Split 2-0 MASH with Dual Digital Error Correction
Author
Zhang, Zhenyong ; Steensgaard, Jesper ; Temes, Gabor C. ; Wu, Jian-Yi
Author_Institution
Oregon State Univ., Carlsbad
fYear
2007
Firstpage
242
Lastpage
243
Abstract
A dual-path 2-0 cascaded (MASH) ADC was implemented with fast digital correction of both DAC errors and MASH mismatch errors. The split structure allows fast convergence and improved accuracy for the correction. Using a 20 MHz clock, the prototype chip achieved an 84 dB dynamic range in a 1.25 MHz signal band, when fabricated in CMOS 0.18 mum process.
Keywords
CMOS integrated circuits; delta-sigma modulation; error correction; CMOS process; DAC errors; digital correction; dual-path cascaded ADC; size 0.18 mum; split 2-0 MASH mismatch errors; Circuit noise; Clocks; Convergence; Dynamic range; Error correction; Multi-stage noise shaping; Noise cancellation; Prototypes; Quantization; Signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location
Kyoto
Print_ISBN
978-4-900784-05-5
Electronic_ISBN
978-4-900784-05-5
Type
conf
DOI
10.1109/VLSIC.2007.4342735
Filename
4342735
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