DocumentCode
1570974
Title
A scalable systolic array architecture for 2D discrete wavelet transforms
Author
Chen, Jijun ; Bayoumi, Magdy A.
Author_Institution
Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
fYear
1995
Firstpage
303
Lastpage
322
Abstract
A systematic synthesis approach has been developed for scalable systolic array architecture for a 2D discrete wavelet transform (DWT) based on the data dependence analysis and linear index space transformation. The proposed architecture has regular topology, local routing, simple controller and high throughput rate. It can be easily extended to different parameters of various levels, macroblocks and filters. The derived architecture has been prototyped using Cadence Edge Framework
Keywords
VLSI; data compression; image coding; systolic arrays; transforms; wavelet transforms; 2D discrete wavelet transforms; Cadence Edge Framework; VLSI; data dependence analysis; image compression; linear index space transformation; local routing; macroblocks; regular topology; scalable systolic array architecture; systematic synthesis approach; throughput rate; Control system synthesis; Data analysis; Discrete wavelet transforms; Filters; Prototypes; Routing; Systolic arrays; Throughput; Topology; Wavelet analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Signal Processing, VIII, 1995. IEEE Signal Processing Society [Workshop on]
Conference_Location
Sakai
Print_ISBN
0-7803-2612-1
Type
conf
DOI
10.1109/VLSISP.1995.527501
Filename
527501
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