Title :
A 21-GHz Fractional-N Synthesizer in 130-nm CMOS
Author :
Ding, Yanping ; Kenneth, K.O.
Author_Institution :
Florida Univ., Gainesville
Abstract :
A 21-GHz fractional-N PLL was demonstrated in 130-nm CMOS. The PLL consumes 19.6 mW power from a 1.2-V supply. The locking range is from 19 to 21.6 GHz, and the frequency resolution is 10 ppm. The measured in-band phase noise at 50-kHz offset and out-of-band phase noise at 20 MHz offset are -67.8 and -121 dBc/Hz.
Keywords :
CMOS digital integrated circuits; frequency synthesizers; phase locked loops; phase noise; CMOS; fractional-N PLL; frequency 21 GHz; frequency resolution; in-band phase noise; out-of-band phase noise; phase locked loop; power 19.6 mW; size 130 nm; voltage 1.2 V; Circuit optimization; Frequency conversion; Frequency synthesizers; Noise measurement; Phase locked loops; Phase measurement; Pulse generation; Tuning; Varactors; Voltage-controlled oscillators;
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
DOI :
10.1109/VLSIC.2007.4342744
