Title :
A Scalable 5-15Gbps, 14-75mW Low Power I/O Transceiver in 65nm CMOS
Author :
Balamurugan, Ganesh ; Kennedy, Joseph ; Banerjee, Gaurab ; Jaussi, James E. ; Mansuri, Mozhgan ; Mahony, Frank O. ; Casper, Bryan ; Mooney, Randy
Author_Institution :
Intel Corp., Hillsboro
Abstract :
This paper presents a scalable low power I/O transceiver in 65 nm CMOS capable of 5-15 Gbps operation over 8" FR4 with power efficiencies between 3-5 mW/Gbps. Nonlinear power-performance tradeoff is achieved by the use of scalable transceiver circuit blocks and joint optimization of the supply voltage, bias currents and driver power. Low power operation is enabled by passive equalization through inductive link termination, active continuous-time RX equalization, global TX/RX clock distribution with on-die transmission lines, and low noise offset-calibrated receivers.
Keywords :
CMOS integrated circuits; equalisers; transceivers; transmission lines; 65 nm CMOS; active continuous-time RX equalization; bit rate 5 Gbit/s to 15 Gbit/s; global TX-RX clock distribution; inductive link termination; joint optimization; low noise offset-calibrated receiver; nonlinear power-performance; on-die transmission lines; passive equalization; power 14 mW to 75 mW; scalable low power I-O transceiver; scalable transceiver circuit blocks; size 65 nm; Bandwidth; Clocks; Delay; Driver circuits; Energy management; Inductors; Power system management; Sampling methods; Transceivers; Voltage; I/O; low power; parallel link; power management; scalable circuits;
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
DOI :
10.1109/VLSIC.2007.4342746
