An 11 Gb/s 2.4 mW Half-Rate Sampling 2-Tap DFE Receiver in 6Snm CMOS

Author

Rylyakov, Alexander

Author_Institution

IBM, Yorktown Heights

fYear

2007

Firstpage

272

Lastpage

273

Abstract

A 2-tap DFE receiver, implemented in a standard digital 65 nm bulk CMOS process, is aggressively optimized for low power and area. The 0.22 mW/Gbps power/speed ratio of the receiver and core area of 30 mum times 40 mum are achieved by using a half-rate architecture, a sampling front end, soft-decision direct feedback equalization and rail-to-rail CMOS clocking. At 11 Gb/s (2.6mA from 0.9V supply), the BER is less than 10^-14 with a PRBS7 test sequence passing through a 30" channel (15dB of loss at 5.5GHz).

Keywords

CMOS integrated circuits; MMIC; decision feedback equalisers; integrated circuit design; integrated circuit testing; low-power electronics; microwave receivers; radio receivers; DFE receiver; PRBS7 test sequence; bit rate 11 Gbit/s; bulk CMOS process; current 2.6 mA; frequency 5.5 GHz; half-rate sampling; low power receivers; power 2.4 mW; rail-to-rail CMOS clocking; sampling front end; size 65 nm; soft-decision direct feedback equalization; voltage 0.9 V; Bit error rate; Circuits; Clocks; Decision feedback equalizers; Inverters; Latches; Power cables; Power dissipation; Sampling methods; Testing; DFE; high speed I/O; receiver;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-05-5

Electronic_ISBN

978-4-900784-05-5

Type

conf

DOI

10.1109/VLSIC.2007.4342747

Filename

4342747