DocumentCode
1571149
Title
A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector
Author
Liang, Che-Fu ; Hwu, Sy-Chyuan ; Liu, Shen-Juan
Author_Institution
Nat. Taiwan Univ, Taipei
fYear
2007
Firstpage
274
Lastpage
275
Abstract
A jitter-tolerance-enhanced 10 Gb/s clock/data recovery (CDR) is presented. By using a gated-digital-controlled oscillator (GDCO), the proposed GDCO-based phase detector achieves a wide linear range and its jitter tolerance is enhanced without sacrificing the jitter transfer. It has been fabricated in 0.13 um CMOS technology and consumes 60 mW from a 1.5 V supply.
Keywords
CMOS digital integrated circuits; jitter; low-power electronics; phase detectors; synchronisation; CMOS technology; GDCO-based phase detector; bit rate 10 Gbit/s; clock-data recovery; gated-digital-controlled oscillator; jitter-tolerance-enhanced CDR; power 60 mW; size 0.13 mum; voltage 1.5 V; Bandwidth; CMOS technology; Circuit testing; Clocks; Frequency measurement; Jitter; Phase detection; Phase frequency detector; Semiconductor device measurement; Solid state circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location
Kyoto
Print_ISBN
978-4-900784-05-5
Electronic_ISBN
978-4-900784-05-5
Type
conf
DOI
10.1109/VLSIC.2007.4342748
Filename
4342748
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