Title :
Clocked semi-floating-gate pseudo differential pair for low-voltage analog design
Author :
Berg, Y. ; Mirmotahari, O.
Author_Institution :
Dept. of Inf., Univ. of Oslo, Oslo, Norway
Abstract :
In this paper we present an ultra low-voltage pseudo differential pair based on a clocked semi floating-gate transistor. The clocked semi floating-gate transistors are exploited to increase the current level for ultra low supply voltages and may be used in ultra low voltage mixed signal design. The pseudo differential pair may operate at supply voltages down to 250 mV. Simulated data for 90 nm CMOS process with a transistor threshold voltage equal to 250 mV is included.
Keywords :
CMOS analogue integrated circuits; MOSFET; analogue circuits; low-power electronics; CMOS process; clocked semi floating-gate transistor; low-voltage analog design; size 90 nm; ultra low voltage mixed signal design; ultra low-voltage pseudo differential pair; voltage 250 mV; Analog circuits; CMOS logic circuits; CMOS process; CMOS technology; Circuit simulation; Clocks; Low voltage; MOS devices; MOSFETs; Threshold voltage;
Conference_Titel :
Circuit Theory and Design, 2009. ECCTD 2009. European Conference on
Conference_Location :
Antalya
Print_ISBN :
978-1-4244-3896-9
Electronic_ISBN :
978-1-4244-3896-9
DOI :
10.1109/ECCTD.2009.5275021
