A Delay Locked Loop Synchronization Scheme for High Frequency Multiphase Hysteretic DC-DC Converters

Author

Li, Pengfei ; Bashirullah, Rizwan ; Hazucha, Peter ; Karnik, Tanay

Author_Institution

Univ. of Florida, Gainesville

fYear

2007

Firstpage

26

Lastpage

27

Abstract

This paper reports a delay locked loop (DLL) based hysteretic controller for high-frequency multiphase buck DC-DC converters. The DLL control loop employs the switching frequency from a hysteretic comparator to automatically synchronize the remaining phases. A dedicated duty cycle control loop is used to enable current sharing and ripple cancellation. We demonstrate a 25-70 MHz 4-phase converter with fast hysteretic control and output conversion range of 17%-80% while achieving a peak efficiency of 83% and peak-to-peak ripple within 10% in standard 0.6 mum 5 V CMOS process.

Keywords

CMOS integrated circuits; DC-DC power convertors; delay lock loops; synchronisation; current sharing; delay locked loop synchronization scheme; efficiency 83 percent; frequency 25 MHz to 70 MHz; high frequency multiphase hysteretic DC-DC converters; hysteretic comparator; ripple cancellation; size 0.6 mum; switching frequency; voltage 5 V; Clocks; DC-DC power converters; Delay; Frequency conversion; Frequency synchronization; Hysteresis; Proportional control; Signal generators; Switching frequency; Voltage control; CMOS; DC-DC converter; hysteretic; multiphase;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-05-5

Electronic_ISBN

978-4-900784-05-5

Type

conf

DOI

10.1109/VLSIC.2007.4342752

Filename

4342752