Title :
Clocked semi-floating-gate ultra low-voltage current multiplier
Author :
Berg, Y. ; Mirmotahari, O.
Author_Institution :
Dept. of Inf., Univ. of Oslo, Oslo, Norway
Abstract :
In this paper we present a ultra low voltage current mode multiplier. The current multiplier is based on a clocked semi floating gate design strategy used for ultra low voltage digital and analog design. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offset voltages are used to shift the effective threshold voltage of the evaluating transistors. A current multiplier able to operate at supply voltages below 200 mV is presented and simulated data are provided. The simulated data presented are obtained using the Spectre simulator provided by Cadence and valid for a 90 nm CMOS process.
Keywords :
CMOS analogue integrated circuits; current-mode circuits; low-power electronics; multiplying circuits; CMOS process; Spectre simulator; clocked semi floating gate design; digital-and-analog design; size 90 nm; threshold voltage; ultra low-voltage current mode multiplier; Analog circuits; CMOS analog integrated circuits; CMOS logic circuits; CMOS process; CMOS technology; Circuit simulation; Clocks; Low voltage; MOSFETs; Threshold voltage;
Conference_Titel :
Circuit Theory and Design, 2009. ECCTD 2009. European Conference on
Conference_Location :
Antalya
Print_ISBN :
978-1-4244-3896-9
Electronic_ISBN :
978-1-4244-3896-9
DOI :
10.1109/ECCTD.2009.5275022
