Hardware implementation of recursive algorithms

The paper presents new results in the hardware implementation and optimization of recursive sequential and parallel algorithms using the known and a new model of a hierarchical finite state machine. Applicability and advantages of the proposed methods are confirmed through numerous examples of the designed hardware circuits that have been analyzed and compared. The results of experiments and FPGA-based prototyping demonstrate clearly that the proposed innovations enable the required hardware resources to be decreased achieving at the same time better performance of recursive sorting algorithms compared to known implementations both in hardware and in software.