Use of increased transistor gate length for leakage reduction in caches

Leakage is a growing issue with the advancements of technologies. It is a predominant problem of on chip caches of microprocessors. The cache is a major portion of the microprocessor area. Further, the SRAM cell is a significant contributor of transistor leakage power. This paper analyses leakage-delay trade-off for increase of the transistor gate length in the on chip cache at 22nm, 32nm and 45nm technology nodes. In 45nm technology node a gain in leakage reduction of over 13.7% can be achieved with a penalty of 0.3% increase in delay by increasing the gate length by 1nm. Similarly leakage reduction of over 38% can be achieved with additional delay of 27.2% in 22nm technology.