A modified complex K-best scheme for high-speed hard-output MIMO detectors

The current literature lacks the VLSI realization of high-order multiple-input-multiple-output (MIMO) detectors in the complex domain, which finds applications in advanced wireless standards such as WiMAX and Long Term Evolution (LTE) systems. In this paper, a novel modified complex K-Best algorithm and its VLSI implementation for a 4 × 4, 64QAM complex MIMO detector are proposed. The main contributions of this paper are the modified hard-output complex K-Best algorithm as well as its efficient architecture, which is well-suited for a pipelined VLSI implementation. By using an efficient fast multiplier and applying both fine-grain pipelining and coarse-grain pipelining to the architecture of the MIMO detector, an improved critical path is obtained, which results in a higher throughput. Complexity analysis and the synthesis results in a 0.18 μm CMOS technology show that compared to the reported VLSI implementations in both the real domain and complex domain, the proposed architecture achieves the highest reported throughput. The proposed architecture is fully in parallel with a fixed critical path independent of the constellation order, which can result in a throughput up to 1 Gbps.