DocumentCode
1571260
Title
A 14-Gb/s 32 mW AC coupled receiver in 90-nm CMOS
Author
Hossain, Masum ; Carusone, Anthony Chan
Author_Institution
Toronto Univ., Toronto
fYear
2007
Firstpage
32
Lastpage
33
Abstract
This paper introduces a high-speed AC coupled receiver architecture for high density interconnects. The proposed architecture combines a novel hysteresis circuit path and a linear broadband amplifier path to recover a NRZ signal from an 80-fF capacitively coupled channel. Using this dual path technique, a 90-nm CMOS prototype achieves 14-Gb/s operation while consuming 32 mW from a 1.2-V supply. The measured sensitivity of the receiver is better than 100 mVp-p differential.
Keywords
CMOS integrated circuits; integrated circuit interconnections; receivers; wideband amplifiers; AC coupled receiver; CMOS; NRZ signal; bit rate 14 Gbit/s; capacitively coupled channel; high density interconnects; linear broadband amplifier; power 32 mW; size 90 nm; Broadband amplifiers; CMOS process; Capacitance; Clocks; Coupling circuits; Hysteresis; Integrated circuit interconnections; Optical signal processing; Prototypes; Pulse amplifiers;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location
Kyoto
Print_ISBN
978-4-900784-05-5
Electronic_ISBN
978-4-900784-05-5
Type
conf
DOI
10.1109/VLSIC.2007.4342754
Filename
4342754
Link To Document