Leakage control in full adders with selectively stacked inverters

Technology scaling beyond the 65nm regime has resulted in leakage power consumption emerging as a major design constraint. Several methods aiming at mitigating leakage power have been studied and tested. These include power-rail gating, input vector control, transistor body biasing, transistor stacking, etc. This paper extends the idea of transistor stacking but limiting it to the inverters in the given logic circuit or cell in order to obtain leakage savings. Stacking of inverters is effective in leakage current reduction during both the active and standby modes of the circuit. Stacking also has the advantage of not requiring any additional control circuitry. We examine the leakage power and delay variations for this approach and compare it with the method of power-rail gating. The results indicate that selective stacking of inverters can yield considerable leakage savings without causing significant delay penalties. Therefore it is suitable for cells such as full adders which are in the critical path of complex logic modules such as the microprocessor.