XOR evaluation for 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier

This paper evaluates four designs of XOR employing our previously presented two-phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. 2PASCL XOR, which demonstrates the lowest power dissipation, is used for the 4 × 4-bit array 2PASCL multiplier. From our simulation results, at transition frequencies of 1 to 100 MHz, the 4 × 4-bit array 2PASCL multiplier shows a maximum of 55% reduction in power dissipation to that of a static CMOS.