Title :
A 5.1GHz 0.34mm2 Router for Network-on-Chip Applications
Author :
Vangal, Sriram ; Singh, Arvind ; Howard, John ; Dighe, S. ; Borkar, N. ; Alvandpour, Atila
Author_Institution :
Intel Corp., Hillsboro
Abstract :
A five-port two-lane pipelined packet-switched router core with phase-tolerant mesochronous links forms the key communication fabric for an 80-tile network-on-chip (NoC) architecture. The 15FO4 design combines 102 GB/s of raw bandwidth with low fall-through latency of 980 ps. A shared crossbar architecture with a double-pumped crossbar switch enables a compact 0.34 mm2 router layout. In a 65nm eight-metal CMOS process, the router contains 210K transistors and operates at 5.1GHz at 1.2 V, while dissipating 945 mW.
Keywords :
CMOS integrated circuits; integrated circuit layout; network routing; network-on-chip; packet switching; NoC architecture; double-pumped crossbar switch; eight-metal CMOS process; five-port two-lane pipelined packet-switched router core; frequency 5.1 GHz; network-on-chip; phase-tolerant mesochronous links; power 945 mW; shared crossbar architecture; size 65 nm; time 980 ps; voltage 1.2 V; Bandwidth; Circuits; Clocks; Delay; Network-on-a-chip; Power measurement; Silicon; Sleep; Switches; Tiles;
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
DOI :
10.1109/VLSIC.2007.4342758
