A novel soft error mitigation approach for SRAM-based FPGAs

SRAM-based FPGA devices are susceptible to Single Event Effects (SEE) inside configuration memory. Most approaches for soft error mitigation use Triple Modular Redundancy (TMR) to avoid the consequences of these errors. The drawback is that TMR implementation results in a triplication of required hardware and therefore TMR increases the power consumption. This paper describes a novel approach of soft error mitigation technique for SRAM-based Field Programmable Gate Arrays without using the Triple Modular Redundancy approach. Based on additional logic storing the correct states, it is capable of detecting Single Event Upsets (SEUs), reconfiguring the system and to correct the detected errors via rollback to the last known correct state. The approach was implemented as a prototype and this paper describes the first results of our research and shows that it is possible to mitigate soft errors in a efficient way but not with the same safety level TMR does.