Title :
A Design Methodology Realizing an Over GHz Synthesizable Streaming Processing Unit
Author :
Ueno, Kiyoji ; Murakami, Hiroaki ; Yano, Naoka ; Okuda, Ryubi ; Himeno, Toshihiko ; Kamei, Takayuki ; Urakawa, Yukihiro
Author_Institution :
Toshiba Corp., Kawasaki
Abstract :
A 7.07 mm2 synthesizable streaming processing unit (SPU) is fabricated in a 65 nm CMOS technology with 8 level copper layers. It is migrated from its original custom design to a synthesizable design to get higher design portability. New features are a new floor plan, height optimized standard cell library, local clock generator cloning and adaptive wire width control. Its logic area is 30% smaller than the full custom designed SPU in the same process generation. Correct functional operation is realized in 4 GHz at 1.4 V.
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; integrated circuit design; logic design; microprocessor chips; ASIC; CMOS technology; SPU; adaptive wire width control; frequency 4 GHz; local clock generator; size 65 nm; synthesizable streaming processing unit design; voltage 1.4 V; Adaptive control; CMOS process; CMOS technology; Clocks; Cloning; Copper; Design methodology; Libraries; Programmable control; Wire; CMOS; Cell; SPE; SPU; synthesizable design;
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
DOI :
10.1109/VLSIC.2007.4342761
