A systematic design procedure for CMOS three-stage NMC amplifiers

This paper presents a new time-domain design procedure for CMOS three stage amplifiers with nested Miller compensation. The optimal design issues of power dissipation are considered to achieve the lowest power consumption while satisfying the required design specifications such as the DC gain, settling time, and noise budget. These parameters are critical for switched-capacitor applications. HSPICE simulation results are provided for a three-stage single-ended class A amplifier to verify the efficiency of the proposed design technique.