Title :
A 2-GHz Direct Sampling Delta-Sigma Tunable Receiver with 40-GHz Sampling Clock and on-chip PLL
Author :
Chalvatzis, T. ; Dickson, T.O. ; Voinigescu, S.P.
Author_Institution :
Univ. of Toronto, Toronto
Abstract :
This paper presents a 2-GHz tunable direct sampling DeltaSigma receiver with 40-GHz sampling clock and on-chip PLL, fabricated in a production 130-nm SiGe BiCMOS process. The measured SFDR and SNDR are 59 dB and 59.84 dB, respectively, over a bandwidth of 60 MHz, and the effective number of bits (ENOB) equals 9.65. Compared to the case where an external low-noise 40-GHz clock was used, no SNDR degradation was observed when the on-chip VCO and PLL were employed. The entire receiver with PLL occupies an area of 1.58 times 2.39 mm2 and consumes 2.19 W when powered from a 2.5-V supply.
Keywords :
BiCMOS integrated circuits; Ge-Si alloys; MIMIC; UHF integrated circuits; delta-sigma modulation; phase locked loops; receivers; semiconductor materials; BiCMOS process; SFDR; SNDR; SiGe; bandwidth 60 MHz; direct sampling delta-sigma tunable receiver; external low-noise clock; frequency 2 GHz; frequency 40 GHz; noise figure 59 dB; noise figure 59.84 dB; on-chip PLL; on-chip VCO; power 2.19 W; sampling clock; size 130 nm; voltage 2.5 V; Bandwidth; BiCMOS integrated circuits; Clocks; Degradation; Germanium silicon alloys; Phase locked loops; Production; Sampling methods; Silicon germanium; Voltage-controlled oscillators;
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
DOI :
10.1109/VLSIC.2007.4342763
