A 2.2 Gb/s DQPSK Baseband Receiver in 90-nm CMOS for 60 GHz Wireless Links

Author

Chen, Minghui ; Chang, Mau-Chung Frank

Author_Institution

Univ. of California at Los Angeles, Los Angeles

fYear

2007

Firstpage

56

Lastpage

57

Abstract

This paper presents a CMOS DQPSK direct-conversion baseband receiver that can deliver 2.2 Gb/s data rate to support 1920times1080 interlaced HDTV wireless transmission in the unlicensed 60 GHz band. The receiver system architecture and major circuit blocks are described. Implemented in the 90 nm CMOS process, the receiver achieves a maximum data rate of 2.4 Gb/s with measured BER of 10^-9. It is operated under IV DC supply voltage with 85 mW of total power consumption.

Keywords

CMOS integrated circuits; differential phase shift keying; error statistics; high definition television; quadrature phase shift keying; radio links; radio receivers; BER; DQPSK baseband receiver; HDTV wireless transmission; bit rate 2.2 Gbit/s; bit rate 2.4 Gbit/s; direct-conversion baseband receiver; frequency 60 GHz; size 90 nm; wireless links; Bandwidth; Baseband; Circuits; Clocks; Demodulation; Energy consumption; Ethernet networks; HDTV; Phase locked loops; Quadrature phase shift keying; bang-bang PLL; baseband; differential QPSK; direct-conversion receiver; multi-level clock recovery;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-05-5

Electronic_ISBN

978-4-900784-05-5

Type

conf

DOI

10.1109/VLSIC.2007.4342764

Filename

4342764