Hardware/software co-simulator for ASIC DSP chips

A hardware/software co-simulator has been developed for a video processing SOC. The simulator is composed of a PC and a FPGA board. The simulator realizes seamless connection between software on a PC and hardware circuits in a FPGA chip. Therefore, partial VLSI design is possible within the software. As modification on both software system and FPGA circuits are easy and as the simulation speed is about the same to that of system program in a high level language, simultaneous optimization of system architecture and LSI design becomes possible. The effective use of the simulator is shown by the partial implementation of an image enhancement system as an example.