Improved FSMD partitioning for low power using Plackett-Burman

Finite State Machine with Datapath (FSMD) partitioning is an effective technique for isolating circuit components. The isolated components can be clock gated or power gated to achieve dramatic power savings. FSMD partitioning typically relies on a highly complex, parameterized model, making the impact of the various tunable parameters hard to understand, leading to suboptimal partitions. In this paper, we use the Plackett and Burman experiment design methodology, which provides a statistically rigorous approach, to study a technique which uses simulated annealing to efficiently partition a FSMD for power gating. A better understanding of the effects of the various parameters allows the partitioning model to be robustly tuned towards optimality.