Noise margin-optimized ternary CMOS SRAM delay and sizing characteristics

This paper presents the design and simulation of a ternary CMOS SRAM cell. A 16 × 16 ternary SRAM with ternary-compatible addressing was designed in a 0.18 μm process and the rise and fall delays were compared with a 16 × 16 binary SRAM. The ternary SRAM was created using cross-coupled ternary inverters. The inverters were optimized for high noise-margins and the optimum transistor sizings were presented. SPICE simulation was performed to compare the delay characteristics of the binary and ternary inverters and SRAM arrays. SPICE simulations confirmed correct functional behaviour of the READ and WRITE operations. The READ delay of the ternary SRAM was comparable to that of the binary counterpart for all cases except for the fall time from {2}⇔{1} while the WRITE delay favoured the binary SRAM by a small amount.