DocumentCode
1571548
Title
A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter
Author
Savoj, Jafar ; Abbasfar, Aliazam ; Amirkhany, Amir ; Jeeradit, Metha ; Garlepp, Bruno W.
Author_Institution
Rambus Inc., Los Altos
fYear
2007
Firstpage
68
Lastpage
69
Abstract
A 12-GS/s 8-bit Digital-to-Analog Converter (DAC) enables 24 Gb/s signaling over conventional backplane channels. Designed in a 90-nm CMOS process, the circuit occupies an area of 670 mum times 350mum and achieves INL and DNL of 0.31 and 0.28 LSB. Measured SNDR and SFDR are 41 dB and 51 dB at 750 MHz and 32.5 dB and 35 dB at 1.5 GHz. The power dissipation is 190 mW from 1-V and 1.8-V power supplies.
Keywords
CMOS integrated circuits; UHF integrated circuits; digital-analogue conversion; DAC; DNL; INL; LSB; SFDR; SNDR; bandwidth 750 MHz; bit rate 24 Gbit/s; digital-to-analog converter; frequency 1.5 GHz; phase-calibrated CMOS converter; power 190 mW; size 90 nm; voltage 1 V; voltage 1.8 V; Backplanes; CMOS process; Clocks; Delay lines; Digital-analog conversion; Frequency synchronization; Linearity; Multiplexing; Power dissipation; Routing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location
Kyoto
Print_ISBN
978-4-900784-05-5
Electronic_ISBN
978-4-900784-05-5
Type
conf
DOI
10.1109/VLSIC.2007.4342769
Filename
4342769
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