DocumentCode :
1571622
Title :
Investigation of Increased Multi-Bit Failure Rate Due to Neutron Induced SEU in Advanced Embedded SRAMs
Author :
Georgakos, Georg ; Huber, Peter ; Ostermayr, Martin ; Amirante, Ettore ; Ruckerbauer, Franz
Author_Institution :
Infineon Technol. AG, Neubiberg
fYear :
2007
Firstpage :
80
Lastpage :
81
Abstract :
This paper reports a dramatically increased multi-bit failure rate due to neutron induced single event upset (SEU) in 65 nm triple-well embedded SRAMs. Based on detailed fail-pattern analysis and circuit simulation a novel failure model is developed and relaxed ECC guidelines are derived.
Keywords :
CMOS memory circuits; SRAM chips; failure analysis; integrated circuit reliability; CMOS circuits; advanced embedded SRAM; fail-pattern analysis; multibit failure rate; neutron induced single event upset; Error correction; Failure analysis; Guidelines; Interleaved codes; Neutrons; Random access memory; Single event upset; Solids; Testing; Voltage; CMOS; SER and neutron; SEU; embedded SRAM; multi-bit; triple-well;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
Type :
conf
DOI :
10.1109/VLSIC.2007.4342774
Filename :
4342774
Link To Document :
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