A low-power double edge-triggered flip-flop with transmission gates and clock gating

In recent years, energy saving techniques have become critical in hardware designs, especially for mobile devices. This paper has reviewed several previous designs of double edge-triggered flip-flops, and has proposed a transmission-gate-based double edge-triggered flip-flop with a clock-gating function. Comparing to the previous work of double edge-triggered flip-flops, the proposed one saved 33.14% power on average (switching activity factor = 0-0.4) and it can save up to 97.85% power compared to conventional single edg-etriggered flip-flops when the input is idle. In addition, the proposed design also improved performance by reducing Clk-to-Q latency by 0.21 ns.