Design and noise analysis of 8Gb/s capacitive low power and high speed 4-PWAM transceiver

In this paper, capacitive 4-PWAM transmitter architectures and circuits are proposed and its bit error rate is estimated by developing noise model considering random jitter, data dependent jitter, and PVT variations. A novel technique is proposed to reduce power and to increase speed by using capacitive driven low swing transceiver. To implement 4-PWAM transmitter new phase controller and adaptive capacitance network are designed. At receiver side, new architectures for PWM and PAM demodulation are proposed and designed. The proposed design saves 1.74~2.4x power and 4x higher data rate than conventional designs.