Efficient undo-redo with incremental netlist to schematic generation

An electronic designer makes incremental changes during the design process in order to explore the design space. Incremental generation of circuit schematic is desirable to avoid schematic regeneration of large electronic design when only few modules of a design are modified. The need of a designer to visualize the initial state of a design before the changes and the subsequent state of a design after the changes creates the functional requirement of undo-redo in schematic generation. The proposed algorithm creates an efficient undo infrastructure along with incremental schematic generation which provides consistent views on undo-redo.