• DocumentCode
    1571693
  • Title

    Hardware implementations of denormalized numbers

  • Author

    Schwarz, Eric M. ; Schmookler, Martin ; Trong, Son Dao

  • Author_Institution
    IBM Server Div., Poughkeepsie, NY, USA
  • fYear
    2003
  • Firstpage
    70
  • Lastpage
    78
  • Abstract
    Denormalized numbers are the most difficult type of numbers to implement in floating-point units. They are so complex that some designs have elected to handle them in software rather than hardware. This has resulted in execution times in the tens of thousands of cycles, which has made denormalized numbers useless to programmers. This does not have to happen. With a small amount of additional hardware, denormalized numbers and underflows can be handled close to the speed of normalized numbers. We will summarize the little known techniques for handling denormalized numbers. Most of the techniques discussed have only been discussed in filed or pending patent applications.
  • Keywords
    floating point arithmetic; number theory; denormalized numbers; filed patent applications; floating-point unit; hardware implementation; normalized numbers; Digital arithmetic; Hardware;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Arithmetic, 2003. Proceedings. 16th IEEE Symposium on
  • ISSN
    1063-6889
  • Print_ISBN
    0-7695-1894-X
  • Type

    conf

  • DOI
    10.1109/ARITH.2003.1207662
  • Filename
    1207662