Minimizing clocking patterns of Adjustable safe clocking for timing variation-aware datapaths

This work focuses on the timing variation-aware datapath design based on Contra-Data-Direction (CDD) clocking. Although a register assignment based on CDD clocking has been proposed, resultant datapaths suffer from the increase in registers. To overcome the problem, this paper proposes a novel timing variation-aware design using Adjustable CDD (ACDD) clocking, named ACDD-based design. An ILP-based approach is presented to minimize the cost of ACDD clocking, which is a fundamental problem in ACDD-based design. Experiments show the effectiveness of the approach.