A unidirectional bit serial systolic architecture for double-basis division over GF(2m)

A unidirectional bit serial systolic architecture for division over Galois field GF(2^m) is presented which uses both triangular and polynomial basis representations. It is suitable for hardware implementations where the dimension of the field is large and may vary. This is the typical case for cryptographic applications. This architecture is simulated in Verilog-HDL and synthesized for a clock period of 1.4 ns using Synopsys. The time and area complexities are truly linear, since no carry propagation structures are present, and the complexity measures are equivalent or excel the best designs proposed so far.