Title :
Ultra low-voltage Delay Locked Loop using carbon nanotubes
Author :
Ajit, J.S. ; Kim, Yong-Bin
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
Abstract :
Carbon Nanotube FET technology is investigated to implement ultra low-voltage DLL and simulation results show that operation at supply voltage as low as 0.3 V is possible with a peak jitter of 13 ps and lock is acquired in 7 cycles with a clock frequency range from 330 MHz to 10 GHz. The characteristics is dependent on the nanotube parameters and the optimum nanotube diameter is found to be 1.35 nm.
Keywords :
carbon nanotubes; carbon nanotubes FET technology; clock frequency range; frequency 330 MHz to 10 GHz; optimum nanotube diameter; peak jitter; size 1.35 mm; supply voltage; time 13 ps; ultra low-voltage DLL; ultra low-voltage delay locked loop; Carbon nanotubes; Delay;
Conference_Titel :
Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-7771-5
DOI :
10.1109/MWSCAS.2010.5548708
