A high-speed swing reduced driver suitable for current-steering digital-to-analog converters

A driver circuit with a reduced swing to serve as a gate driver for steering switches of current-steering digital-to-analog converters (DACs) is designed. The swing reduced driver (SRD) reduces the digital signal feedthrough to the output node of the converter by decreasing the voltage swing at the gates of the switching transistors. The proposed SRD is suitable for operation at high speed. The circuit can be designed to maintain the voltage swing in the desired range without compromising seriously the area of the digital circuit. The designed circuit is validated through simulations of an application designed using the AMS 0.35 mum CMOS process parameters.