Title :
A medium-grain reconfigurable processing unit
Author :
Van Dyken, Jason ; Delgado-Frias, José G.
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
Abstract :
In this paper the components required to implement a central processing unit (CPU) and its arithmetic logic unit (ALU) are presented using a novel medium grain reconfigurable hardware architecture. The CPU can be configured to match the application´s requirements in terms of word-size, number and type of units, and instruction set. The MIPS instruction set has been used to show the potential of the processing unit. The clock for this implementation is calculated to be in the order of 2GHz for current technologies.
Keywords :
instruction sets; multiprocessing systems; reconfigurable architectures; ALU; CPU; MIPS instruction; arithmetic logic unit; central processing unit; instruction set; medium grain reconfigurable processing unit; reconfigurable hardware architecture; Central Processing Unit; Clocks; Communication system control; Computer architecture; Computer science; Digital arithmetic; Digital signal processing; Hardware; Read-write memory; Reconfigurable logic;
Conference_Titel :
Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-7771-5
DOI :
10.1109/MWSCAS.2010.5548714
