DocumentCode
1572199
Title
A new high speed, low power adder; using hybrid analog-digital circuits
Author
Taherinejad, Nima ; Abrishamifar, Adib
Author_Institution
Electr. Eng. Dept., Iran Univ. of Sci. & Technol., Tehran, Iran
fYear
2009
Firstpage
623
Lastpage
626
Abstract
In this paper a new high speed and low power adder is presented. The circuit uses a hybrid concept of analog and digital circuit design to propagate the carry and so achieve a Full Adder with 78 ps delay and 7.26 muW of power consumption. SPICE Simulations performed on the 0.18 mum TSMC Technology demonstrates the average improvement of 159%, 184% and 516%, respectively for delay, power consumption and PDP.
Keywords
SPICE; adders; high-speed integrated circuits; low-power electronics; mixed analogue-digital integrated circuits; SPICE simulation; TSMC Technology; full adder; high speed circuits; hybrid analog-digital circuits; low power adder; power 7.26 muW; size 0.18 mum; time 78 ps; Added delay; Adders; Analog-digital conversion; Circuit simulation; Circuit synthesis; Delay effects; Digital circuits; Energy consumption; Propagation delay; SPICE; Full Adder; High Speed; Hybrid Analog-Digital Circuit Design; Low Power;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuit Theory and Design, 2009. ECCTD 2009. European Conference on
Conference_Location
Antalya
Print_ISBN
978-1-4244-3896-9
Electronic_ISBN
978-1-4244-3896-9
Type
conf
DOI
10.1109/ECCTD.2009.5275072
Filename
5275072
Link To Document