VLSI chip design of a CORDIC-based adaptive lattice filter

This work describes a 16-bit fixed-point VLSI chip design of an adaptive lattice filter (ELF) which is suitable for linear prediction or AR modeling with a filter order up to sixteen. The adaptation algorithm is based on the Burg algorithm, and the chip design employs the CORDIC arithmetic. The chip can operate in three modes. With the multi-stage single chip mode, the lattice filtering and adaptation operations are done recursively each time a new input data arrives. With the multi-stage multi-chip mode, cascading multiple identical chips can extend the filter to a higher desired order. With the single-stage multi-chip mode, L chips can be connected as a pipeline to form a L-stage lattice filter with each chip serving as one lattice stage. This mode can achieve a highest filtering speed of 1.7 M samples/sec. Besides, in implementing the Burg algorithm, a practical computing scheme is used such as to avoid internal overflow and improve the numerical accuracy