A statistical approach for design and testing of analog circuitry in low-cost SoCs

A novel design-for-testability approach is proposed, which is derived from the aggressive probabilistic targets set forth for the yield and quality to be achieved in the massproduction of high-volume low-cost transceiver SoCs, thus requiring solutions that are fundamentally different from the traditional approaches. Statistical analysis is presented as the basis for the proposed approach, and specific guidelines are defined and demonstrated through examples. The proposed approach, based on built-in-self-testing (BIST) of RF/mixed-signal functions in the transceiver SoC, relies on digital processing resources that are typically available within the SoC at no additional cost and may aid in its testing and calibration. The important roles of characterization and built-in-self-calibration and compensation in this context are also defined.