DocumentCode
1572553
Title
Design validation of ZCSP with SPIN
Author
Beaudenon, Jean-Lou ; Encrenaz, Emmanuelle ; Desbarbieux, J.-L.
Author_Institution
UPMC, Paris, France
fYear
2003
Firstpage
102
Lastpage
110
Abstract
We consider the problem of specifying a model of the zero copy secured protocol for the purpose of LTL verification with the SPIN model checker. ZCSP is based on direct memory access. Data is directly read/written in user space memory, decreasing latency and saving processor computing time. We first introduce the ZCSP protocol before analysing different ways of modelling it. Two main steps were performed: a finite and a nonfinite sequences model. The first model gave us an overview of the protocol robustness. The second allowed us to test realistic properties. We also describe LTL properties that were checked with the SPIN model checker. Unfortunately, the size of the system was frequently prohibitive. Thus, we explain all minimization steps we had to perform: variables´ domains restriction, interleaving reduction, realistic environment representation by fairness constraints.
Keywords
file organisation; formal verification; minimisation; protocols; temporal logic; LTL verification; SPIN model checker; ZCSP; design validation; direct memory access; domain restriction; linear temporal logic; processor computing time; protocol robustness; realistic property testing; sequence model; user space memory; zero copy secured protocol; Access protocols; Automata; Delay; Interleaved codes; Logic design; Message passing; Read-write memory; Robustness; State-space methods; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Application of Concurrency to System Design, 2003. Proceedings. Third International Conference on
Print_ISBN
0-7695-1887-7
Type
conf
DOI
10.1109/CSD.2003.1207704
Filename
1207704
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