6-bit low-power subranging-ADC with increased throughput

This paper describes a high-speed low-power subranging Flash ADC designed in 90nm Mixed-Mode CMOS process. The maximum speed of subranging-ADC is limited by the time taken for the fine-ADC reference to settle. The proposed method splits optimally the total time taken for the coarse-ADC and fine-ADC comparisons to achieve the maximum possible clock speed. An auxiliary track-and-hold has been used in the interleaved track-and-hold to introduce 1/2 clock-cycle delay. Simulations results show that the subranging-ADC achieves SFDR of 37.7 dB at sampling rate of 1.54GS/s for 360MHz input and dissipates 15 mW power from 1-V supply. It has 4.6 ENOB @ Nyquist and FoM of 0.4 pJ/conv. step. Minimum-size devices have been used in the comparator to achieve low-power. A digital offset calibration method has been used to reduce the offset of comparators.